1. Field of the Invention
The present invention relates to semiconductor devices composed of field effect transistors (hereinafter referred to as FET) of metal-insulator semiconductors (hereinafter referred to as MIS) stacked to one another, and more specifically relates to stacked MIS devices composed of a pair of N-type MIS-FET and P-type MIS-FET stacked to each other with a common gate electrode.
2. Description of the Related Art
This type of stacked MIS device has been used in memory cells such as static random access memory (hereinafter referred to as SRAM), which needs high integration density. FIGS. 3(a), 3(b) and 3(c) illustrate one example of the conventional stacked MIS device in which the device is formed of an inverter circuit as shown in FIG. 3(a).
Namely, as indicated in FIG. 3(a), numeral 1 refers to a power terminal held at a potential level of a power supply and numeral 2 refers a grounding terminal held at a grounding potential. A P-type MIS-FET 5 and an N-type MIS-FET 6 are serially connected between the power terminal 1 and the grounding terminal 2. The gate electrodes of those MIS-FET's 5 anc 6 are commonly connected to an input terminal 4. Similarly, their drain electrodes are commonly connected to an output terminal 3. An input signal applied to the input terminal 3 is inverted by the FET's 5 and 6 to be derived at the output terminal 4.
For such inverting operation, the gate electrodes of both FET's 5 and 6 are supplied with the same input signal through the input terminal 3. Therefore, it is better to form the gate electrodes of both FET's 5 and 6 with a single conductive layer having a single region which operates as both gate electrodes. For realizing such gate structure, a stacked MIS device has been devised.
FIG. 3(b) is a schematic plan view of this conventional stacked MIS device, and FIG. 3(c) is a schematic sectional view of the same taken along line D-D of FIG. 3(b). In these figures, an N-type source region 32 and an N-type drain region 33 of the N-type MIS-FET 6 are formed in a P-type semiconductor substrate 31 such as Si. A gate insulating film 34 is formed on the semiconductor substrate 31, between the source and drain regions 32 and 33 and a gate electrode 35 is formed on the gate insulating film 34 to thereby constitute the N-type MIS-FET 6. Further, another gate insulating film 36 is formed on the gate electrode 35 and an N-type semiconductor film 39 such as polycrystalline Si is formed on the gate insulating film 36. Thereafter, a P-type source region 37 and a P-type drain region 38 are formed in the semiconductor film 39 to thereby constitute a P-type MIS-FET 5 together with the aforementioned gate electrode 35.
However, in the above described stacked MIS device of the conventional type, the source and drain regions 32 and 33 of N-type MIS-FET 6 are aligned along the common gate electrode 35 in the same direction as those of source and drain regions 37 and 38 of P-type MIS-FET 5. Therefore, when the channel length of the N-type MIS-FET 6 is to be reduced, the channel length of the P-type MIS-FET 5 is correspondingly needed to be reduced. However, when reducing the dimensions of MIS-FETs in order to increase the integration density of the device, the lower MIS-FET 6 may have different limit in reducing its dimension than that of the upper MIS-FET 5. In such case, the possible reduction of dimension is determined by the critical limit of one MIS-FET which is greater than the dimensional limit of the other MIS-FET. Namely, in such case that the upper P-type MIS-FET 5 is composed of a semiconductor film made of a poly-crystalline silicon or made by re-crystalization of the poly-crystalline silicon, which has a considerable limit in reducing the dimension thereof, the channel length of the lower N-type MIS-FET 6 must be reduced in registration with that of the upper MIS-FET 5.
In order to improve the performance of inverter circuit as shown, for example, in FIG. 3(a), it is needed to reduce the channel length of N-type MIS-FET 6 as small as possible. However, as described above, the possible minimum channel length of N-type MIS-FET 6 is controlled by greater minimum channel length of P-type MIS-FET 5, thereby failing to improve the total performance of device.